Skip to main content

Best lockdown routine

I am student form an IIT. I am here to share best way how to stay fit and improve knowledge with energetic schedule so here we go.
The very first thing is to wake up early after that morning exercise stretching gym running.

                  

     

 After having breakfast meditate for a while to improve mental strength further we should go with our task or aim what ever we want to achieve 
                                                   



After having or daily task complete we should have bit interaction with our friends to improve our communication skills.


Comments

Post a Comment

Leave comment for any queries

Popular posts from this blog

MATLAB code for phase modulation

  Theory Phase modulation is a modulation pattern for conditioning communication signals for transmission.  In phase modulation carrier signal phase changes w.r.t message signal.                                                                                        MATLAB Code fm = 1000; fc =10*10^3; Am = 1; K=2*pi*5; Ac = 1; Tm = 1/fm; Tc = 1/fc; t = 0:Tm/999:2*Tm; %message signal plot modulating_signal = Am*sin(2*pi*fm*t); subplot(2,1,1); plot(t, modulating_signal); grid on; title('message signal'); xlabel('time'); ylabel('amplitude') %phase modulation signal plot with Am=5 y1=Ac*cos(2*pi*fc*t+K*modulating_signal); subplot(2,1,2); plot(t,y1); grid on; title('phase Modulated signal'); xlabel('time'); ylabel('amplitude') ...
Post a Comment
Read more

Designing a 8X1 MUX using logic gates in Verilog. Verilog code and test bench.

Circuit Diagram Verilog Code module MUX_8x1 ( output Y, input A,B,EN, input [2:0] SEL); assign Y=EN&((A&B)&(~SEL[0]&~SEL[1]&~SEL[2])|(A|B)&(~SEL[0]&~SEL[1]&SEL[2])|(~A)&(~SEL[0]&SEL[1]&~SEL[2])|(~B)&(~SEL[0]&SEL[1]&SEL[2])|(~(A&B))&(SEL[0]&~SEL[1]&~SEL[2])|~(A|B)&(SEL[0]&~SEL[1]&SEL[2])|(~A&B|A&~B)&(SEL[0]&SEL[1]&~SEL[2])|(A&B|~A&~B)&(SEL[0]&SEL[1]&SEL[2])); endmodule                                                                     Test bench `timescale 1ns / 1ps module MUX_8x1_tb; // Inputs reg A; reg B; reg EN; reg [2:0] SEL; // Outputs wire Y; MUX_8x1 uut ( .A(A),  .B(B),  .EN(EN),  .SEL(SEL),  .Y(Y) ); initial begin // Initialize In...
1 comment
Read more
My Countdown   Trouble of oscillating neutral is to  provide each  of the  transformers  with a third or ...  system  can continue to operate in  open - delta  or in  V  −  V  although with reduced available capacity. ...  connected balanced load  at 0.8  power factor   lagging . ... A  load  of 1000  kVA  at  0.866 p.f. lagging  is  supplied  by  two 3 phase  transform-.
Post a Comment
Read more