Designing a 8X1 MUX using logic gates in Verilog. Verilog code and test bench.

Circuit Diagram

Verilog Code

module MUX_8x1 (

output Y,

input A,B,EN,

input [2:0] SEL);

assign Y=EN&((A&B)&(~SEL[0]&~SEL[1]&~SEL[2])|(A|B)&(~SEL[0]&~SEL[1]&SEL[2])|(~A)&(~SEL[0]&SEL[1]&~SEL[2])|(~B)&(~SEL[0]&SEL[1]&SEL[2])|(~(A&B))&(SEL[0]&~SEL[1]&~SEL[2])|~(A|B)&(SEL[0]&~SEL[1]&SEL[2])|(~A&B|A&~B)&(SEL[0]&SEL[1]&~SEL[2])|(A&B|~A&~B)&(SEL[0]&SEL[1]&SEL[2]));

endmodule

                                                                    Test bench

`timescale 1ns / 1ps

module MUX_8x1_tb;

// Inputs

reg A;

reg B;

reg EN;

reg [2:0] SEL;

// Outputs

wire Y;

MUX_8x1 uut (

.A(A), 

.B(B), 

.EN(EN), 

.SEL(SEL), 

.Y(Y)

);

initial begin

// Initialize Inputs

A = 1'b0;

B = 1'b0;

EN= 1'b1;

SEL= 3'b111;

// Wait 10 ns for global reset to finish

#10;

A = 1'b0;

B = 1'b1;

EN= 1'b1;

SEL= 3'b011;

        

#10;

A = 1'b1;

B = 1'b1;

EN= 1'b1;

SEL= 3'b100;

#10;

A = 1'b0;

B = 1'b0;

EN= 1'b1;

SEL= 3'b001;

      

end

      

endmodule